The ever increasing need for high performance and increased chip (integrated circuit or IC) functionality with lower costs has resulted in aggressive scaling of transistor dimensions. As transistor dimensions are scaled down, the effect of parameter variations on circuit robustness increases. Increased process variations result in lower circuit performance and can potentially lead to functional/parametric failures degrading manufacturing yield.
Process variations can be classified into distinct categories: process variations can be “inter-die” or “intra-die;” and process variations can also be “random” or “systematic.” An inter-die process variation is a process variation across multiple dies. An intra-die process variation is a process variation across a single die. A systematic process variation is one that exhibits a systematic correlation with some parameter. A random process variation is one that does not exhibit any meaningful correlation. Thus, you can have four process variation cases, inter-die random, inter-die systematic, intra-die random, or intra-die systematic.
Hence, it is important to monitor/track the effect of process variations and to tune the process for improving the manufacturing yield.